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DESCRIPTION:   'Title: hls4ml - Open Source Machine Learning Accelerators o
 n FPGAs\n   When: Saturday\, Aug 13\, 14:00 - 15:55 PDT\n   Where: Caesars
  Forum - Council Boardroom (Demo Labs) - [1]Map\n   Speakers:Ben Hawks\,An
 dres Meza\n\n   SpeakerBio:Ben Hawks\n   Ben Hawks is an AI Researcher at 
 Fermi National Accelerator\n   Laboratory\, focusing on optimizing and com
 pressing neural networks to\n   be tiny\, fast\, and accurate for use on F
 PGAs and other specialized\n   hardware. Since he was young\, he’s had a
  personal interest in\n   computer security\, programming\, and electronic
 s\, and is interested in\n   learning how to make machine learning fair\, 
 efficient\, and fast.\n   Outside of work\, he spends his time messing wit
 h electronics\, tabletop\n   RPGs\, and catering to the whims of a small f
 eline overlord.\n\n   SpeakerBio:Andres Meza\n   Andres Meza is a research
  and development engineer in the Department\n   of Computer Science and En
 gineering at the University of California\,\n   San Diego. He received a B
 .S. Computer Science and a B.S. Cognitive\n   Science with a Machine Learn
 ing and Neural Computation Specialization\n   from UCSD in 2020. His curre
 nt research focuses on hardware security\,\n   optimization of ML models f
 or hardware deployment\, and computer\n   vision.\n\n   Description:\n   B
 orn from the high energy physics community at the Large Hadron\n   Collide
 r\, hls4ml is an open-source Python package for machine learning\n   infer
 ence in FPGAs (Field Programmable Gate Arrays). It creates\n   firmware im
 plementations of machine learning algorithms by translating\n   traditiona
 l\, open-source machine learning package models into\n   optimized high le
 vel synthesis C++ that can then be customized for\n   your use case and im
 plemented on devices such as FPGAs and Application\n   Specific Integrated
  Circuits (ASICs). Hls4ml can easily scale the\n   implementation of a mod
 el to take advantage of the parallel processing\n   capabilities that FPGA
 s offer\, not only allowing for low latency\, high\n   throughput designs\
 , but also designs sized to fit on lower cost\,\n   resource constrained h
 ardware. Hls4ml also supports generating\n   accelerators with different d
 rivers that build minimal\, self-contained\n   implementations which enabl
 e control via Python or C/C++ with little\n   extra development or hardwar
 e expertise.\n\n   Audience: Hardware\, AI\, IoT\, FPGA\n\n   '\n\n   1. h
 ttps://defcon.outel.org/consolidated_page.html#CaesarsSummitBR\n\n\n
DTEND:20220813T225500Z
DTSTART:20220813T210000Z
LOCATION:DL - Caesars Forum - Council Boardroom (Demo Labs)
SUMMARY:hls4ml - Open Source Machine Learning Accelerators on FPGAs
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